Stress memorization techniques (SMT) have been proven to work on planar complementary metal oxide semiconductor (CMOS) technologies such as n-channel field effect transistors (NFETs). By imparting stress into the transistors during fabrication, increased electron mobility is experienced. In general, SMT processes on NFETs involve transferring stress from a high-stress nitride to the source and drain regions of the NFETs by way of a high-temp anneal, and then stripping the high-stress nitride.
The traditional SMT procedure, however, is unlikely to work for future generation CMOS technologies that involve a FINFET structure. A FINFET device typically includes a source region and a drain region interconnected by a plurality of fins which serve as a channel region of the device. A gate surrounds at least a portion of each of the fins in between the source and drain regions. Epitaxy is typically used to merge the fins in the source and drain regions. The traditional SMT procedure is likely not suitable for use in FINFET devices because, unlike planar devices, in FINFETs the channel runs along the sidewalls of the fins. Thus, the channel will be a distance away from any high-stress nitride when deposited on the merged epitaxial source and drain regions.
Therefore, improved SMT techniques for use with FINFET devices would be desirable.